1. Field of the Invention
The present invention relates to a semiconductor memory device. In particular, the present invention relates to a semiconductor memory device of which power consumption in a standby state can be reduced. More particularly, the present invention relates to a configuration for reducing standby current of a semiconductor memory device that includes redundancy circuitry for repairing a defective memory cell through replacement with a redundant or spare memory cell. Furthermore, the present invention relates to a testing method of a low power consumption semiconductor memory device.
2. Description of the Background Art
FIG. 51 schematically shows a configuration of a memory cell of a static random access memory (SRAM).
In FIG. 51, the memory cell includes a pair of cross coupled P-channel MOS transistors (insulated gate field effect transistors) PQ1 and PQ2 for pulling up, a pair of cross coupled N-channel MOS transistors NQ1 and NQ2 for data storage, and a pair of accessing N-channel MOS transistors NQ3 and NQ4.
P-channel MOS transistor PQ1 is electrically coupled between a memory cell power supply line MVCC and a node ND1, and has a gate electrically coupled to a node ND2. P-channel MOS transistor PQ2 is electrically coupled between memory cell power supply line MVCC and node ND2, and has a gate electrically coupled to node ND1.
N-channel MOS transistor NQ1 is electrically coupled between node ND1 and a memory cell ground line MVSS, and has a gate electrically coupled to node ND2. N-channel MOS transistor NQ2 is electrically coupled between node ND2 and memory cell ground line MVSS, and has a gate electrically coupled to node ND1.
N-channel MOS transistor NQ3 turns ON, in response to the potential of a signal on a word line WL, to electrically couple node ND1 to a bit line BL. N-channel MOS transistor NQ4 selectively turns ON, in response to the potential of the signal on word line WL, to electrically couple node ND2 to a complementary bit line ZBL.
In the SRAM cell shown in FIG. 51, MOS transistors PQ1 and NQ1 form a CMOS (complementary MOS) inverter. Also, MOS transistors PQ2 and NQ2 form a CMOS inverter. MOS transistors PQ1, PQ2, NQ1, and NQ2 form a CMOS inverter latch circuit.
Data complementary to each other are stored at nodes ND1 and ND2. in the SRAM cell, in a data storage mode, a current path of transferring electric current between memory cell power supply line and MVCC memory cell ground line MVSS via nodes ND1 and ND2 is cut off. Thus, the power consumption can be reduced.
The memory cell shown in FIG. 51 is generally called a xe2x80x9cfull CMOS memory cellxe2x80x9d. Compared to a configuration including pull-up load elements provided to nodes ND1 and ND2, the configuration of the full CMOS memory cell is superior in operational performance and low power consumptionability. For these reasons, the full CMOS memory cells are generally widely used in low power consumption SRAMs.
FIG. 52 schematically shows a plan layout of the SRAM cell shown in FIG. 51. In FIG. 52, since the SRAM cell is the full CMOS cell, there is provided an n-well region for forming P-channel MOS transistors PQ1 and PQ2, and a p-well region for forming N-channel MOS transistors NQ1 and NQ2. In the n-well region, there are formed active regions AA1 and AA2 in which P-channel MOS transistors PQ1 and PQ2 are formed, respectively. Active regions AA1 and AA2 are each formed in an L-shape to be symmetric with respect to a central line vertically extending in between, as viewed in FIG. 52. Active regions AA1 and AA2 are used as p-type impurity regions. On the other hand, in the p-well region, active regions AA3 and AA4 are formed in which N-channel MOS transistors NQ1 and NQ2 are formed, respectively. Active regions AA3 and AA4 are each formed in a reversed L-shape to be symmetric with respect to a center line in between. Active regions AA3 and AA4 are used as n-type impurity regions.
A gate electrode interconnection line GA1 is formed across horizontally-extending regions of active regions AA1 and AA3. On the other hand, a gate electrode interconnection line GA2 is formed across horizontally-extending regions of active regions AA2 and AA4. Gate electrode interconnection lines GA1 and GA2 are formed of, for example, polysilicon interconnection lines. In addition, a gate electrode interconnection line GA3 is formed across vertically extending regions of active regions AA3 and AA4. Gate electrode interconnection line GA3 is electrically coupled to a word line.
Each of gate electrode interconnection lines GA1 and GA2 has a region extending horizontally toward a central region. Gate electrode interconnection line GA1 forms gate electrodes of MOS transistors PQ1 and NQ3. Similarly, gate electrode interconnection line GA2 forms gate electrodes of MOS transistors PQ2 and NQ4, and gate electrode interconnection line GA3 forms gate electrodes of MOS transistors NQ3 and NQ4.
Local interconnection lines LI1 to LI7 are formed electrically coupling MOS transistors PQ1, PQ2, NQ1, NQ2, NQ3, and NQ4 from one another. Local interconnection lines LI1 to LI7 are formed through a borderless process with respect to active regions AA1 to AA4. Local interconnection lines LI1 to LI5 are formed above active regions AA1 to AA4, and are electrically coupled directly to corresponding active regions AA1 to AA4. Specifically, local interconnection line LI1 electrically couples active regions AA1 and AA2 with each other. Similarly, local interconnection line LI2 electrically couples active regions AA1 and AA3 with each other, and local interconnection line LI3 electrically couples active regions AA2 and AA5 with each other.
Local interconnection line LI2 corresponds to node ND1 shown in FIG. 51, and local interconnection line LI3 corresponds to node ND2 shown in FIG. 51. Local interconnection lines LI1 to LI7 are individually formed in self alignment with gate electrode interconnection lines GA1 to GA3, and no contacts are formed in the portions in which local interconnection lines LI2 and LI3 overlap with gate electrode interconnection lines GA1 and GA2. After the gate electrode interconnection lines are formed, the gate electrode interconnection lines are used as a mask, and the local interconnection lines are formed. In this process, the gate electrode interconnection lines are covered with an insulation film, and the contact holes are formed in portions for the contact with the local interconnection lines. Therefore, in the portions in which the gate electrode interconnection lines overlap with the local interconnection lines, the insulation film is formed on the gate electrode interconnection lines, and no contacts are formed for the local interconnection lines and the gate electrode interconnection lines.
Local interconnection line LI2 is electrically coupled to gate electrode interconnection line GA2 via a contact hole CH1. Similarly, local interconnection line LI3 is electrically coupled to gate electrode interconnection line GA1 via a contact hole CH2.
On the other hand, local interconnection line LI4 is electrically coupled via a contact hole CH3 to a first level metal interconnection line ML1 formed vertically extending on an upper layer. Also, local interconnection line LI5 is electrically coupled via a contact hole CH4 to a first level metal interconnection line ML4 formed on an upper layer thereof First level metal interconnection line ML4 corresponds to memory cell ground line MVSS, and transfers ground voltage. Also, local interconnection lines LI6 and LI7 are electrically coupled via a contact hole CH5 to a first level metal interconnection line ML2 formed linearly extending in the vertical direction as viewed in the drawing. Also, local interconnection line LI7 is electrically coupled via a contact hole CH6 to a first level metal interconnection line ML3 formed linearly extending on an upper layer thereof. First level metal interconnection lines ML2 and ML3 form bit lines BL and ZBL, respectively.
Contact holes CH3 to CH6 are formed in self alignment with gate electrode interconnection lines GA1 to GA3. Also, local interconnection lines LI4 to LI7 are formed in self alignment with gate electrode interconnection lines GA1 to GA3. In this arrangement, contact holes CH3 to CH6 and local interconnection lines LI4 to LI7 can be formed at minimum pitches.
Gate electrode interconnection line GA2 is electrically coupled via contact hole CH1 to local interconnection line LI2. Also, gate electrode interconnection line GA1 is electrically coupled via contact hole CH2 to local interconnection line LI3. Local interconnection lines LI2 and LI3 are formed, respectively, in self-alignment with gate electrode interconnection lines GA1 and GA2. In this configuration, no contacts are formed in portions in which local interconnection lines LI2 and LI3 overlap with gate electrode interconnection lines GA1 and GA2. Contact holes CH1 and CH2 are used to electrically couple local interconnection lines LI2 and LI3 to gate electrode interconnection lines GA2 and GA1, respectively.
Local interconnection line LI1 is electrically coupled via a second level metal interconnection line (not shown) to memory cell power supply line MVCC disposed extending in the row direction.
In the layout of the memory cell of a vertically long type shown in FIG. 52, bit lines BL and ZBL and memory cell ground lines MVSS are first metal interconnection lines, and are disposed parallel in a common metal layer. As the miniaturization of memory cells progresses, the distances between first level metal interconnection lines ML2 and ML3 and first level metal interconnection lines ML1 and ML4 are reduced, resulting in an increased probability of occurrence of short circuits between bit lines BL and ZBL and memory cell ground lines MVSS.
Memory cell power supply line MVCC is disposed extending parallel to word line WL and perpendicular to bit line BL.
In the memory cell having the layout as shown in FIG. 52, when a short circuit occurs because of adhesion or adsorption of particles in a manufacturing step, an operational failure is caused. In addition, electric current flows even in a standby state through the short circuit. That is, although defectively operating memory cells are replaced by redundant cells, the defect itself remains thereat. As long as a defect exists, during standby, electric flows through the short circuit, thereby increasing the standby current. The following is the types of short circuits that can be considered to occur in the above-described configuration.
(1) Short circuit between the nodes; (2) Short circuit between a node and the memory cell power supply line; (3) Short circuit between a node and the memory cell ground line; (4) Short circuit between a node and a word line; (5) Short circuit between a node and a bit line; (6) Short circuit between bit lines; (7) Short circuit between a word line and a memory cell power supply line; (8) Short circuit between a bit line and a memory cell ground line; and (9) Short circuit between a memory cell power supply line and a memory cell ground line. During standby, the bit line is precharged to the level of power supply voltage, and the word line is maintained at the ground voltage level.
In particular, in the layout of the memory cell of a vertically long type as shown in FIG. 52, among the types of short circuits listed above, the short circuit between a bit line and a memory cell ground line can occur at a very high probability. This is because first level metal interconnection lines ML2 and ML3 (which form bit lines BL and ZBL) and first level metal interconnection lines ML1 and ML4 (which form memory cell ground lines MVSS) are disposed parallel to each other at minimum design dimensions.
In the full CMOS memory cell configured of the six MOS transistors shown in FIG. 51, when one of the aforementioned short circuits (1) to (9) occurs, a path allowing electric current to flow always exist because complementary data are stored at nodes ND1 and ND2. Thus, there is caused a standby current defect.
A state is considered in which, as shown in FIG. 53, a resistance component RZ exists, due to a particle or the like, between nodes ND1 and ND2 at which complementary data are stored. When the resistance value of resistance component RZ is sufficiently low, nodes ND1 and ND2 are short circuited, and can not store data accurately. Consequently, the memory cell is determined to be defective.
During standby, since word line WL is in an unselected state, and the voltage is kept at a LOW level, MOS transistors NQ3 and NQ4 stays in the OFF state. A case is now assumed that, as shown in FIG. 53, a node ND1 is at a HIGH level, and node ND2 is at a LOW level. In this case, MOS transistors PQ1 and NQ2 are each in the ON state, and MOS transistor PQ2 and NQ1 are each in the OFF state. Accordingly, there is formed a path through which electric current flows from memory cell power supply line MVCC to memory cell ground line MVSS via MOS transistor PQ1, resistant component RZ, and MOS transistor NQ2.
Suppose that the resistance value of resistance component RZ is larger than that of an ON-resistance of each of MOS transistors PQ1 and NQ2. In this case, nodes ND1 and ND2 are maintained at a HIGH level and a LOW level, respectively, and data are stored at nodes ND1 and ND2 accurately. That is, when the resistance value of resistance component RZ is relatively large, the memory cell causes a standby current defect, although it does not cause an operational defect.
As described above, the higher the power supply voltage applied through memory cell power supply line MVCC, the lower the ON-resistance of each of the memory cell transistors. Thereby, the resistance value of resistance component RZ is relatively increased, and a state in which the memory cell causes a standby current defect, but does not cause an operational defect becomes even more enhanced.
Generally, in a semiconductor memory device of a large storage capacity, in order to improve the yield, redundant memory cells are provided to replace a defective memory cell that does not normally operate. The following procedure is carried out to replace a defective memory cell with a redundant memory cell. The address corresponding to a defective memory cell is first identified. Then, a fuse in a redundant program circuit is blown off by using an energy beam such as a laser beam. Thereby, the address corresponding to the defective memory cell is programmed, and the defective memory cell is maintained in a normally unselected state.
When the address corresponding to the defective memory cell is designated, the redundant memory cell is addressed in accordance with the address of the defective memory cell programmed in the redundant program circuit. Consequently, the defective memory cell is replaced with the redundant memory cell.
As described above, the memory cell, which does not cause an operational defect while it cause a standby current defect, causes the standby current to increase. That is, this memory cell is a defective memory cell reducing the product yield of the memory device because the specification value of the standby current can not be satisfied due to the increased standby current. Such a defective memory cell will be referred to as xe2x80x9cstandby-current-defective but normally-operable memory cellsxe2x80x9d hereinbelow. However, since the standby-current-defective but normally-operable memory cells normally operate, the address thereof could not be identified through a normal testing.
In a conventional detection method for detecting a standby-current-defective but normally-operable memory cell described above, the following procedure is carried out. Testing is performed in a state in which the memory cell power supply voltage is lowered below that used in a normal operation state. In this state, since the ON-resistance of each of the memory cell transistors is increased according to the drop in the gate voltage, the resistance value of resistance component RZ is relatively small. Thereby, the memory cell that causes a standby-current defect but normally operates under the normal power supply voltage is forced into a defective operation state. Under this condition, the testing is performed. As a result, the address of the standby-current-defective but normally-operable memory cell is identified, and the standby-current-defective but normally-operable memory cell is replaced with the redundant memory cell.
However, since the ON-resistance of each of the memory cell transistors is reduced with the increase in the memory cell power supply voltage, the standby-current-defective but normally-operable state becomes even more enhanced. Therefore, in the method in which the testing is performed in the condition in which the memory cell power supply voltage is lowered below that used in the normal operation state, such a case may occur in which the standby-current-defective but normally-operable state cannot be caused to be revealed. For example, in an event that the resistance value of resistance component RZ is relatively large, even when the ON-resistance of each of the memory cell transistors is increased, data can normally be stored. Consequently, the standby-current-defective but normally-operable memory cell could not be identified. In addition, in this state, the increased ON-resistance causes the standby current to decrease, thereby causing a case in which a standby-current defect does not occur. Moreover, when the testing is performed under the condition in which the memory cell power supply voltage is lowered below that used in a normal operation state, such a case may occur that even normally-operating memory cells are determined to be operation-defective.
As described above, the standby-current-defective but normally-operable state caused due to the adhesion of particles would be caused due to patterning failure. In addition, the aforementioned state similarly occurs not only in short circuit between storage nodes, but also in any one of the aforementioned short circuits (1) to (9).
When a standby-current-defective but normally-operable memory cell is present, the power consumption during standby is increased, and therefore the semiconductor memory device cannot be used for a portable equipment that requires a low standby current.
In order to reliably detect such standby-current defective but normally operable memory cell, it is required to detect the standby current accurately. Moreover, when redundancy replacement is made on a standby-current-defective but normally-operable memory cell, the standby current after the redundancy replacement should be made smaller than a specification value with reliability. Thus, the redundant replacement state is established in a simulated manner to detect the standby current before practical replacement.
An object of the present invention is to provide a semiconductor memory device capable of reliably reducing standby current.
Another object of the present invention is to provide a semiconductor memory device capable of detecting the address of a standby-current-defective but normally-operable memory cell, without exerting an adverse effect on normal memory cells.
Still another object of the present invention is to provide a testing method for a semiconductor memory device capable of reliably reducing standby current by replacing a standby-current-defective but normally-operable memory cell with a redundant memory cell.
A semiconductor memory device according to a first aspect of the present invention includes a plurality of memory cells arranged in rows and columns, a reference potential node for supplying a reference potential, a switch circuit coupled to the reference node and selectively rendered conductive for transmitting the reference potential at the reference node, a first voltage transmission line for transmitting the reference potential received from the switch circuit to the memory cells, and voltage control circuitry activated in a specific operation mode for detecting whether the potential on the voltage transmission line is at a predetermined potential and for setting the potential of the first voltage transmission line to a potential level according to the result of detection in accordance with the result of detection.
A semiconductor memory device according to a second aspect of the present invention includes: a plurality of memory cells arranged in rows and columns; a reference voltage node; a switch circuit coupled to the reference voltage node and selectively rendered conductive for transmitting the voltage at the reference voltage node; a first voltage transmission line for transmitting the voltage received from the switch circuit to the plurality of memory cells; a plurality of bit line pairs, disposed in correspondence with memory cell columns, each having memory cells of a corresponding column connected; a second voltage transmission line for transmitting the reference voltage received from the switch circuit; a bit line load circuit disposed in correspondence with each bit line pair and rendered conductive for transmitting a voltage on the second voltage transmission line to the corresponding bit line pair; a load voltage detection circuit for detecting the voltage on the second voltage transmission line in a specific operation mode and setting the first voltage transmission line to a voltage level according to the detection result; and a switch control circuit for latching the voltage of the first voltage transmission line in the specific operation mode and setting the switch circuit into a conductive/non-conductive state in accordance with the latch result.
A semiconductor memory device according to a third aspect of the present invention includes: a plurality of memory cells arranged in rows and columns; a reference voltage node; a first voltage transmission line connected to the reference voltage node, for transmitting the voltage received from the reference voltage node to the plurality of memory cells; a plurality of bit line pairs, disposed in correspondence with memory cell columns, each having memory cells of a corresponding column connected; a second voltage transmission line for transmitting the voltage received from the reference voltage node; a bit line load circuit disposed in correspondence with each bit line pair and rendered conductive for transmitting a voltage on the second voltage transmission line to the corresponding bit line pair; and a load voltage detection circuit for detecting the voltage level on the second voltage transmission line in a specific operation mode and setting at least the voltage on the first voltage transmission line to a voltage level according to the detection result.
A testing method for a semiconductor memory device according to a fourth aspect of the present invention includes the steps of; writing data to memory cells; maintaining the memory cells in a standby state; in response to a test mode designation, disconnecting a predetermined reference potential node from a voltage transmission line transmitting a predetermined potential to the memory cells; detecting a potential of the voltage transmission line and holding the voltage transmission line to ground potential when the potential of the voltage transmission line is not higher than a prescribed potential level; reading data of the memory cells under the condition of the disconnection; in accordance with the read out data, identifying presence and an address of a defective memory cell if present; and replacing the defective memory cell with a redundant memory cell in accordance with the result of identification.
A testing method according to a fifth aspect of the present invention is provided for a semiconductor memory device having a plurality of memory cells arranged in rows and columns, a plurality of bit line pairs disposed in correspondence with columns and to each of which memory cells of a corresponding column are connected, a first voltage transmission line for transmitting the voltage at a reference power voltage node to the plurality of memory cells, and a second voltage transmission line for transmitting the voltage received from the reference power voltage node to the bit line pairs.
The testing method according to the fifth aspect of the present invention includes the steps of; isolating at least one of the first and second voltage transmission lines from the reference voltage node in accordance with a test mode designation signal; detecting a voltage of at least one of the first and second voltage transmission lines and setting the voltage level of the first voltage transmission line in accordance with the detection result; storing the voltage on the first voltage transmission line; selectively establishing the connection between the reference power voltage node and at least one of the first and second voltage transmission lines in accordance with the stored voltage level; performing writing and reading of test data on the plurality of memory cells and detecting the presence of and an address of a defective memory cell; and programming connection between the reference power voltage node and at least one of the first and second voltage transmission lines in accordance with the detection result and replacing the defective memory cell with a redundant memory cell.
As described above, by selectively disconnecting the first voltage transfer line from the reference potential node, the potential of the first voltage transfer line is lowered by a leakage current when a stand-by current defect exists. Consequently, a determination can be made as to whether a stand-by current defect exists by detecting the potential level of the first voltage transfer line and by setting the potential of the first voltage transfer line according to the detection result.
By detecting the voltage level of the second voltage transmission line for transmitting a voltage to a bit line pair and adjusting, according to the detection result, a voltage level of the first voltage transmission line, even in the case where a normally operable but stand-by current defective short circuit occurs in the second voltage transmission line, by driving the voltage level of the first voltage transmission line to a predetermined voltage level, memory cells associated with the defective bit line pair can be set in an electrically floating state. Consequently, a short circuit failure such as a micro short circuit can be detected with reliability.
As for the circuit for detecting the voltage level of the second voltage transmission line, the detection operation thereof is selectively stopped or allowed to drive the voltage level of the second voltage transmission line in accordance with the detected voltage level of the second voltage transmission line, in response to the operation mode designating signal. Thus, even in the case where a failure causing the second voltage transmission line to be held at an intermediate voltage level exists due to a micro short circuit or the like, the current can be prevented from being consumed due to a through current in the load detection circuit. Accordingly, by detecting the current consumption in the standby state, a stand-by current failure memory cell can be accurately detected. Consequently, a standby current failure can be detected accurately to perform the redundant replacement for repairing the standby current failure. Thus, a semiconductor memory device of a lower current consumption can be implemented.
Furthermore, it can be accurately identified whether the memory cells store the data accurately by reading out data from the memory cells under the state where the first voltage transfer line is maintained at a voltage level according to the detection result. Therefore, the standby-current defective but normally operable memory cell can be set to an operation-defective state and the address thereof can be accurately identified. Through the redundant replacement of the operation-defective memory cell, the standby-current defective but normally operable memory cell can be repaired. In addition, since the first voltage transfer line associated with the standby-current defective but normally operable memory cell is disconnected all the time from the reference potential node, a current path for the leakage current of the standby-current defective but normally operable memory cell can be cut off. Consequently, the standby-current defect can be repaired with reliability.
By latching the voltage of the first voltage transmission line and establishing, according to the latched voltage, the connection state between the reference potential node and the second voltage transmission line, a defective column can be maintained in a failure state with reliability. Even in the case where a short circuit occurs on a word line, the defective word line can be maintained in a non-selected state with reliability when unselected. Thus, a so-called multi-selection of word lines can be prevented with reliability in which a plurality of word lines are erroneously driven into a selected state concurrently. Without causing a block failure that an entire block including a plurality of word lines is determined defective, the defective word line can be specified and repaired with reliability. Particularly, a load of the defective word line is higher due to the short circuit than a load of a normal word line. Therefore, through a function test, the failure can be detected, so that the defective word line can be detected with reliability because the defective word line is slower in voltage change than a normal word line. A so-called cross failure of a defective word line (row) and a defective column due to a short circuit can be accurately detected and repaired through redundant replacement with redundant memory cells, resulting in a reliable repairing of the standby current failure.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.